MOSFET MODELING FOR VISI SIMULATION

MOSFET MODELING FOR VISI SIMULATION

INTRODUCTION OF MOSFET MODELING FOR VISI SIMULATION :

Even though the operation of the modern Metal-Oxide-Semiconductor (MOS) transistor was first described by Lilienfield in 1930 [l], it was not until 1960 that the first MOS transistor using silicon as the semiconductor material was reported by Kang and Atalla [2].

The MOS technology became viable only after methods of routinely growing reliable oxides were developed and reported by Snow, Grove, Deal and Sah in 1964 [3]. Since that time the MOS industry has expanded very quickly. Today MOS integrated circuits (ICs) have emerged as the dominant technology in the semiconductor industry. The exponential growth in the number of com- ponents per chip and projections for the future .

PDF) Evaluation of MOSFETs with crystalline high-k gate ...

Also shown is the minimum feature size that can be produced on a chip. The dotted lines are projections for the future. Clearly with this technology it is now possible to have more than a million transistors on a single chip. All this has been possible due to the fact that the basic MOS transistor size has shrunk by a factor of about 20 during the last two decades, from a feature size of 20pm to less than a micron. Much of this shrinkage can be attributed to advances in lithography, the use of ion implantation, and low temperature annealing.

During the early days of MOS technology, aluminum (Al) gate p-channel MOS transistors were the workhorse technology. In the late sixties poly- silicon replaced A1 as the material for the MOS transistor gate [S]. The next major milestone was the LOCOS (Localized Oxidation of Silicon) isolation technique [6].

Commercially successful products using the NMOS process (all n-channel MOS transistors) with LOCOS isolation were developed in the mid seventies. NMOS device technology became the driving force of the 1970s because of its reliability, reasonable manufacturing cost, and scalability. During the last decade, MOS transistors have been scaled down in dimensions both vertically and horizontally. Rules of this scaling were originally formulated by Dennard et al. [7] in 1974 and subsequently other schemes of scaling were proposed

PDF) Evaluation of MOSFETs with crystalline high-k gate ...

Unfortunately not all device parameters can be scaled proportionately. These limits on scaling have increased the importance of device and circuit modeling. The CMOS (Complementary MOS, with both p- and n-channel transistors) technology has revolutionized the state of the art of IC design due to its inherent noise immunity and reduced static power dissipation.

CMOS technology became the technology of choice for the VLSI (Very Large Scale Integration) chips of the 1980s [9]. Although there has been considerable recent interest in incorporating bipolar transistors into CMOS processes, resulting in a BiCMOS technology [lo, 111, we will restrict our- selves to device modeling for NMOS and CMOS technologies.

PDF) Evaluation of MOSFETs with crystalline high-k gate ...

Although the MOS transistor (also called MOSFET) is the most important device for VLSI chips such as microprocessors and semiconductor memo- ries, it is also becoming an important power device.

MOS transistors based on DMOS (Double-diffused MOS) and VMOS (Vertical grooved MOS) technology have highly asymmetrical characteristics which makes these technologies unsuitable for integrated circuit applications [ 121. Nevertheless, excellent discrete power devices are built with these technolo- gies. The modeling of power MOSFETs is not covered in this book.

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